1. Technical Field
Methods of manufacturing flash memory devices are disclosed.
2. Background of the Related Art
In implementing the flash memory devices, shallow trench isolation (hereinafter called ‘STI’) is employed. In the prior art, as the sidewall oxidization process is employed, a tunnel oxide film formed at the top corner of the trench is formed in thickness thinner than a deposition target. The thickness of the tunnel oxide film formed at the top corner of the trench becomes thinner than that of the tunnel oxide film formed at its center. Furthermore, in order to sufficiently reduce the critical dimension (hereinafter called ‘CD’) in the active region, a photolithography technology of a micro line width is required. For this, expensive equipments are required and the cost price is thus increased. In addition, there are limitations in increasing the surface area of the floating gate and the capacitance value applied to the ONO (oxide/nitride/oxide) film being the dielectric film. Accordingly, it is difficult to expect an increase in the coupling ratio.
Furthermore, in manufacturing the flash memory device, a mask CD is changed and the uniformity of the wafer is poor, in a patterning process for isolating the floating gate. For this reason, it is not easy to implement a uniform floating gate. Accordingly, the coupling ratio is varied and fail occurs in a program or erase operation. Moreover, a mask work becomes more difficult in implementing a spacer of below 0.10 μm in view of a higher-integrated design.
Meanwhile, if the floating gate is not uniformly formed, the difference in the coupling ratio is severe. Accordingly, an over-erase problem occurs in the program or erase operation of the cell, which adversely affects the characteristics of the device. Also, this causes to lower the yield and to increase the cost price due to an increased number of a mask process.
Incidentally, a device fail, etc. occurs due to a moat occurring in the STI or LOCOS process (indicating a shape that the field oxide film around the active region becomes depressed). In view of the above, it is an important problem that must be solved in a high-integrated flash memory device to secure a cell having no moat and increase the coupling ratio.